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Hello all,

Anyone had any success using the Lattice SDRAM controller with the FleaFPGA? I'm trying to setup a very simple system using a Mico8 CPU a PLL and the SDRAM controller and get an error like this...

ERROR - Value INTERNAL for property FEEDBK_PATH on block Mico8/SDRAM/pmi_pll0OFFCLKOP5090MachXO250.0100100100.025.0/PLLInst_0 is invalid.

...which has me stumped. Any ideas?

-- Wayne
(12-10-2014 08:33 AM)wvisser Wrote: [ -> ]Hello all,

Anyone had any success using the Lattice SDRAM controller with the FleaFPGA? I'm trying to setup a very simple system using a Mico8 CPU a PLL and the SDRAM controller and get an error like this...

ERROR - Value INTERNAL for property FEEDBK_PATH on block Mico8/SDRAM/pmi_pll0OFFCLKOP5090MachXO250.0100100100.025.0/PLLInst_0 is invalid.

...which has me stumped. Any ideas?

-- Wayne

Hello Wayne,

Not sure if I've seen your specific error before myself. However...

I have played with Lattice's own SDRAM controller in the past myself, but that did not seem to work for me back then. I have since successfully used other free/open DRAM controller cores for my project examples. That's just what has worked for me of course, your mileage may vary.

For the record, I myself have not used LM8 at all and only very briefly played with the LM32 on FleaFPGA. I have since designed my own lean and mean Sweet32 CPU softcore mainly for use with my FleaFPGA board.

This is only a guess, but perhaps that problem might be caused by some issue with the MicoSystem Builder tools, which you may or may (or not?) be using. Have you tried asking Lattice?

Best regards Valentin
Hi Valentin,

Just a belated follow-up to this problem - I did follow-up with Lattice and they confirmed that there's a problem in one of the Lattice design files (wb_sdr_ctrl.v). This is still the case as of Diamond 3.5. Not yet sure if it's been fixed in 3.6.

Having said that, I still have not gotten the controller to work, even with the corrected file supplied by Lattice. However, at least my design compiles...

I'll keep you posted if I have any success.

-- Wayne
(10-30-2015 11:00 PM)wvisser Wrote: [ -> ]Hi Valentin,

Just a belated follow-up to this problem - I did follow-up with Lattice and they confirmed that there's a problem in one of the Lattice design files (wb_sdr_ctrl.v). This is still the case as of Diamond 3.5. Not yet sure if it's been fixed in 3.6.

Having said that, I still have not gotten the controller to work, even with the corrected file supplied by Lattice. However, at least my design compiles...

I'll keep you posted if I have any success.

-- Wayne

Thanks Wayne for your update. Smile

As you know, I do not use their reference SDRAM controller module due to my own issues with it. All of the HDL examples that were ported to the FleaFPGA board (that exercise the SDRAM), rely on open-source modules that seem to work quite well. For example: Sweet32, Next186 and TG68 include open-sourced DRAM modules.

That said, I would be interested to know if you do find success with it. Thanks again!

Regards Valentin
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