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Full Version: Ohm board redesigned!
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Hello everyone,

Would you believe it?? I'm back! Big Grin

As a result of issues around exotic parts sourcing for the initial Ohm board prototypes (as well as finding some renewed motivation to continue making FPGA-based hardware), I decided to push forward once again and redesign my Ohm board..

[Image: Flea_Ohm_MkII_norm_small.jpg]

As you can see: it is now bigger (though still smaller than my FleaFPGA Classic and Uno boards!), has more (and 32-bit wide) ram and now also comes with more connectivity: 10/100 Ethernet as well as a flex ribbon header.

With luck, I should be able to power this bad boy up (and hopefully working..) around the end of next week. Can't wait! Big Grin

Regards,
Valentin
Great news! I hope testing it will go well Smile
.. and we have a prototype! Big Grin

[Image: flea_ohm_mk2_asy.jpg]

Board powered up without releasing any magic smoke (thankfully). Ported FleaDSO, minimig and Next186 projects to it successfully. Still have some things left to test (like the Ethernet port). However, so far it's looking promising! Smile More to follow..
Very nice board! I hope it is orderable soon Big Grin
Been a loong while since I posted an update. A few things have happened since then Smile

Long story short: after completing a bunch of tests, bugfixes and/or tweaks, I ended up creating two different 2nd-round prototype board designs - one with 10/100 Ethernet and another with Gigabit Ethernet (pictured below, with and without some user accessories installed):

[Image: Flea_Ohm_GbE_small.jpg]

[Image: Flea_Ohm_GbE_2_small.jpg]

Ethernet tests: This one was a pleasant surprise - wasn't expecting my Gigabit variant to work (was still happy to release the 10/100 variant if it did not work..), but work it did! Big Grin Gonna do some more testing on it, but I have decided to upgrade the spec. to include it in the final board..

CSI port testing: Didn't go so well.. After finally getting around to diving into this in a major way, I discovered my solution to be unsatisfactory due to problems with shared i/o pins for csi and parallel camera support Undecided Therefore, I decided to delete the CSI port and instead focus on parallel CMOS camera module functionality (but with the possibility for CSI support via 'SLVS' configuration of suitable GPIO pins)..

Deleting the CSI header did free up more user GPIO pins (which are always welcome.. :-), so I added an extra single-row header strip above GPIO-B to access the extra GPIO to the (hopefully final) PCB design.

Anyway, this now leaves parallel CMOS camera and some GPIO-related tests to carry out. To be continued.. Thanks for reading! :-)
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