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Transport Triggered Architecture
09-11-2014, 02:32 PM
Post: #1
Transport Triggered Architecture
My project is a vision application. I am a total beginner in FPGA's, but from what I have read, transport triggered architecture is the way to go.
Even a very small TTA needs a processor to control.
Any suggestions for a small soft processor?
Any suggestions for the TTA VHDL, starting small and adding function blocks later?
Should I rather use an external processor?
Thank you
Johan Smit
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09-12-2014, 01:57 AM (This post was last modified: 09-12-2014 11:35 AM by Fleasystems.)
Post: #2
RE: Transport Triggered Architecture
Hello Johan,

While I am no expert on machine vision algorithms myself, I'll try my best to answer your questions. However, you will need to elaborate on what it was you were trying to accomplish.

What I do know about Video processing, is that it is a fairly advanced and complex subject to apply with any FPGA. As you've stated you have zero (or near-zero) experience with FPGAs I would suggest you first start off with getting comfortable with using VHDL (or Verilog, though the examples provided in the FleaFPGA downloads section are VHDL). Then go forward with your TTA arch, or RISC CPU + hardwired FFT or whatever your final configuration may be.

There is also the matter of FleaFPGA's logic resources being somewhat limited, which must be taken into account for any digital design (After all, FleaFPGA is intended as an entry-level FPGA dev board). It is possible that for really complex video processing apps you may need to goto a larger and usually more expensive FPGA platform.

As for a main CPU that 'calls the shots' so to speak, there are several on opencores I could recommend you. I do have 68K and x86 ports for FleaFPGA, but those CISC cores to eat up a lot of FPGA fabric and therefore may or may not work out for you..

Alternatively, I could even offer my own 32bit RISC CPU called 'Sweet32' as a possible option. While it only currently has a software assembler available, Sweet32 is a good example of a very simple, yet useful CPU core (please keep a lookout for a detailed post with sources about my Sweet32 RISC CPU over the weekend..).

Again, it all comes back to what you're trying to do Smile

Cheers Valentin
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09-12-2014, 04:49 PM
Post: #3
RE: Transport Triggered Architecture
Thank you for the reply Valentin,
I realize that the project is complicated, but then one eats an elephant one bite at a time. Also this is mostly a hobby project, there is not that much pressure to get done.
Originally I thought to do the project on an ARM micro only, and it is surely possible, but then realized that the sliding window and analysis part of it can be much faster done on an FPGA. With the FPGA then also comes the possibility to include the processor on the FPGA. This may be too ambitious for the XO2. No problem, I already have a small ARM board to do most of the work on, and it can be interfaced to the FPGA. The small processor needed to control the TTA should be in the FPGA, I think. That can then do the wishbone interface and will save a lot of external interface pins.
With only the RAM on FleaFPGA, the sliding window, LBP extraction, TTA processor, and maybe hashing on the FPGA, it will work out, one part at a time.
I am in the meantime testing some algorithms on Pelles C on the computer.
I intend to stay with VHDL, not Verilog.
As an aside, something similar had been done in Australia, http://www.abc.net.au/tv/newinventors/txt/s2271782.htm
There the problem was opening a gate to allow sheep to get to the water, but keep kangaroos out, as the farmer has to transport the water.
That project was done on a PC.
Once I have everything working, one can determine the minimum required in FPGA and processor. I think it will eventually congeal into a FPGA, ARM or high-speed 8051, RAM, and SD card or other long term memory on one board.
In the meantime, thanks, FleaFPGA will allow me to do lots of experimenting and coding.
I will look out for your Sweet32, thank you.
Best Regards
Johan Smit
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09-15-2014, 01:27 PM
Post: #4
RE: Transport Triggered Architecture
Hello Johan,

I think you are more across the background theory than I am. I have to admit, I've not read up on the sliding scale algorithm until now. It does look interesting, though.

Going by that new inventors' episode, it seems like their all their software was doing is creating an outline of the object(s) under study and then performing some geometric comparisons with stored values. Personally, if an Arduino can do outline detection (link shows outline detect only, not subsequent comparison) I do not believe it would be a huge stretch for a decent soft-CPU with some added hardware support to do what you're asking.

As for my own Sweet32 CPU, I have just created a new post about it in the members area. Feel free to check it out. Thanks! Smile

Best regards,
Valentin
PS: It is a shame 'The inventors' show was killed off a while back. I used to watch it almost religiously! So much for progress..
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09-16-2014, 06:01 PM
Post: #5
RE: Transport Triggered Architecture
Thank you. I have looked at Sweet32, and it looks good. I am unsure, however, at this stage if more than a simple state machine is necessary. It will still take time to get there.
From what I have read, the first step is to extract a Local Binary Pattern (LBP) from each pixel, using a sliding window.
The process, using a Transport Triggered Architechture (TTA) is well described in:
APPLICATION-SPECIFIC INSTRUCTION PROCESSOR FOR EXTRACTING LOCAL BINARY PATTERNS.pdf by the Univ. of Oulu, Finland, and other publications. This will be a huge step for me to delve directly into the VHDL, so I am first testing the algorithm on the PC from pictures, using Pelles C. This is the first step, and I intend to progress from there on-wards.
Best Regards
Johan Smit
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